Notes in COSC 3360 Chapter 1

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Status	Last Update	Fields
Published	03/16/2025	Processor
Published	03/16/2025	main memory
Published	03/16/2025	I/O modules
Published	03/16/2025	System bus
Published	03/16/2025	What does the top level view of computer components look like?
Published	03/16/2025	Process-memory
Published	03/16/2025	Processor-I/O
Published	03/16/2025	Data processing
Published	03/16/2025	Control
Published	03/16/2025	Draw out the a basic instruction cycle
Published	03/16/2025	Draw out the characteristics of a hypothetical machine.
Published	03/16/2025	Draw out an example of a program execution.
Published	03/16/2025	Program Interrupt
Published	03/16/2025	Timer Interrupt
Published	03/16/2025	I/O Interrupt
Published	03/16/2025	Hardware failure
Published	03/16/2025	Draw a program control wihtout and with interrupts.
Published	03/16/2025	Draw an instruction cycle with interrupts.
Published	03/16/2025	How does a computing process interrupts put simply?
Published	03/16/2025	Draw what happens in the processor and main memory when an interrupt occurs after an instruction at location N and the return from the interrupt.
Published	03/16/2025	An I/O program consists of what three sections?
Published	03/16/2025	What are the 9 steps in interrupt processing?
Published	03/16/2025	Draw an example of interrupts with sequential processing and interrupts with nested processing.
Published	03/16/2025	What would a time sequence of multiple interrupts look like?
Published	03/16/2025	what are the relationships between the cost per bit, access time, and capacity?
Published	03/16/2025	As one goes down the memory hiearchy, what occurs?
Published	03/16/2025	Draw out the memory Hierarchy
Published	03/16/2025	Formula for the hit ratio
Published	03/16/2025	Hit ratio (definition)
Published	03/16/2025	What is the locality of reference?
Published	03/16/2025	What is secondary or auxiliary memory?
Published	03/16/2025	Illustrate how cache exploits the principle of locality.
Published	03/16/2025	A block of cache memory is made up of what?
Published	03/16/2025	Cache consists of...
Published	03/16/2025	Illustrate the layout of main memory.
Published	03/16/2025	Draw the read and write decision tree for cache.
Published	03/16/2025	What is block size?
Published	03/16/2025	mapping function
Published	03/16/2025	replacement algorithm
Published	03/16/2025	what are the two constraints on the mapping function
Published	03/16/2025	The write policy dictates ...
Published	03/16/2025	programmed I/O
Published	03/16/2025	Interrupt-driven I/O
Published	03/16/2025	What are drawbacks that both program I/O and interrupt-driven I/O suffer from?
Published	03/16/2025	Direct access memory.
Published	03/16/2025	Symmetric Multiprocessors Definition
Published	03/16/2025	What is the permance advantage of SMP organiztion over a uniprocessor organization?
Published	03/16/2025	What is the Availability advantage of a SMP organization over a uniprocessor organization?
Published	03/16/2025	What is the incremental growth advantage of an SMP organization over a uniprocessor organization?
Published	03/16/2025	What is the scaling advantage of an SMP organization over a uniprocessor organization?
Published	03/16/2025	Draw an SMP organization
Published	03/16/2025	What is a muticore or chip multiprocessor?
Published	03/16/2025	DDR3 memory controller
Published	03/16/2025	QuickPath Interconnect (QPI)
Published	03/16/2025	Draw the block diagram of a multicore system (Intel Core i7).
Status	Last Update	Fields