Review Note
Last Update: 12/04/2024 11:20 AM
Current Deck: ethanki::SPCA
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Front
Explain the cache coherency protocol: MSI
Back
- every line in cache has some meta-data (1 of 3 states) Modified, Shared, Invalid
- listen for reads/writes on other processors
- & responds by changing cache line states or get the new data if needed
- every read or write needs to send a notification to the communication bus between the processors → many bus messages
![](paste-73838f2a8e0d783d2b08ea50aa73a68a8f523f03.jpg)
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