Notes in SPCA

To Subscribe, use this Key

Subdecks

Name
Assembly
C

Status	Last Update	Fields
Published	11/04/2024	Name the 3 categories where system software is used & at least one example.
Published	11/04/2024	What is the connection to implementation in Java vs C?
Published	11/04/2024	What does "implementation defined" mean?
Published	11/04/2024	Define what a program is.
Published	11/04/2024	What is the connection/difference between a process and a program?
Published	11/04/2024	Describe the Mark-and-Sweep garbage collection.
Published	11/14/2024	Define the term virus.
Published	11/14/2024	Explain the very generic idea of a buffer overflow bug. (1 sentence)
Published	11/14/2024	How does the representation of floating point numbers work? What is the main limitation?
Published	11/14/2024	What is the numerical form of a floating point (How can we generally describe a fp number)?
Published	11/14/2024	C: What is the difference between single precision and double presicion for floating point representation?
Published	11/14/2024	floating point normalized values - Descibe their encoding.
Published	11/14/2024	floating point denormalized values - Descibe their encoding and meaning.
Published	11/14/2024	floating point special values - Descibe their encoding and meaning.
Published	11/14/2024	Name 4 floating point rounding options.
Published	11/14/2024	How to create the binary representation of a floating point number?
Published	11/14/2024	What is a benchmark?
Published	11/14/2024	What are performance metric(s)?
Published	11/14/2024	What is the CPE-Measurement? (in regards to optimization)
Published	11/14/2024	Give the Formula for Program Execution Time. (in regards to optimization)
Published	11/14/2024	Frank asks you to explain the concept of pipelined hardware, to make sure you don’t forget about him. Imagine a drawing of pipelined hardware.
Published	11/14/2024	What is the hype about “superscalar processors”?
Published	11/14/2024	Define latency.
Published	11/14/2024	Define what's meant by cycles/issue. (in regards to optimization)
Published	11/14/2024	When is performance latency bound and when is it throughput bound?
Published	11/20/2024	What is a cache miss?
Published	11/20/2024	(Cache performance metrics) - Define Miss Rate (Hit Rate)
Published	11/20/2024	(Cache performance metrics) - Define Hit Time
Published	11/20/2024	(Cache performance metrics) - Define Miss Penalty
Published	11/20/2024	Name the 4 types of cache miss? (hint: 4 C's)
Published	11/20/2024	Visualise the general cache organization in terms of S,E,B. Frank is curious what the corresponding cache size is, can you help him?
Published	11/20/2024	Name the steps in a cache read based on SEB structure of cache. (4 steps)
Published	11/20/2024	cache write - What to do on a write-hit? (Name and summarize the 2 options.)
Published	11/20/2024	cache write - What to do on a write-miss? (Name and summarize the 2 options.)
Published	11/20/2024	locality - Why is it important (conceptually)? Name the 2 kinds.
Published	11/20/2024	How to do a cache miss analysis for nested loops?
Published	11/20/2024	Def: What is the control flow of the CPU?
Published	11/20/2024	Def: What is an exception?
Published	11/20/2024	Differentiate between the two things that can result in two kinds of exceptions.
Published	11/20/2024	Name 4 types of exceptions.
Published	11/20/2024	How do exception vectors work?
Published	11/26/2024	What is the basic way of waiting for and dealing with interrupts from the side of the CPU?
Published	11/28/2024	Address spaces - Name and describe the 3 kinds.
Published	11/28/2024	Overview of address translation with a page table (Look at the graphic to get a conceptual overview of the structure and names)
Published	11/28/2024	What are the 3 advantages of Virtual Memory?
Published	11/28/2024	What are the 3 problems of Virtual Memory?
Published	11/28/2024	In summary Virtual Memory is an important tool for the following 4 things:
Published	11/28/2024	(Adress translation in VM) Describe the Process behind a page hit.
Published	11/28/2024	(Adress translation in VM) Describe the Process behind a page fault.
Published	11/28/2024	What is the TLB?
Published	11/28/2024	What’s the formula to calculate needed linear page table size in Virtual Memory?
Published	11/28/2024
Published	12/03/2024	Describe how an L1 cache access works
Published	12/03/2024	Name the 4 Cache addressing schemes
Published	12/04/2024	Define Coherency and Consistency.
Published	12/04/2024	Define “Programm Order” and “Visibility Order”. (Consistency models: terminology)
Published	12/04/2024	Frank has hit his head too hard and forgot what Sequential Consistency is(no worries, he is fine otherwise). Can you help him to define Sequential Co…
Published	12/04/2024	What’s needed to maintain Sequential Consistency? (from the computer perspective)
Published	12/04/2024	Cache coherence with snooping
Published	12/10/2024	Surprise Frank by showing that you also know what makes Processor Concistency special.
Published	12/04/2024	Explain the cache coherency protocol: MSI
Published	12/04/2024	Explain the cache coherency protocol: MESI
Published	12/04/2024	Explain the cache coherency protocol: MOESI
Published	12/04/2024	Explain the cache coherency protocol: MESIF
Published	12/25/2024	(Multiprocessing & Multicore) Barriers and fences - What’s the difference?
Published	12/25/2024	(Multiprocessing & Multicore) Define compiler barriers and memory barriers.
Published	12/25/2024	PPROG HAS TAKEN OVER YOUR ANKI REVIEW SESSION. Describe how a process can acquire and release a lock with TAS or spin on this anki card forever…
Published	12/25/2024	PProg is attacking, choose Test And Test-And-Set to defeat PProg.  Choose your counter attack: 1) Describe what makes the TATAS acquire different…
Published	12/25/2024	PProg wakes you up at 3 AM to ask you to explain CAS conceptually. You should know this in your sleep.
Published	12/25/2024	“Mamma Mia!”- ABBA has a big Problem… Someone stole one of their B’s. Maybe the right place to start your search is the ABA Problem from PProg. When…
Published	12/25/2024	What is Symmetric Multiprocessing (SMP)? What is it’s bottleneck?
Published	12/25/2024	(NUMA) What helpful changes can be made to the basic CPU-Memory-Structure on a Multi core Computer? → Also answer: What does NUMA stand for?
Published	12/25/2024	(NUMA) Cache Coherence - How can it be implemented when there are many network links instead of a universal bus?
Published	12/25/2024	(Multiprocessing) What is the problem with false sharing?
Published	12/26/2024	(Devices) How can the values in a device register change?
Published	12/26/2024	(Devices) What are the 2 options for addressing registers?
Published	12/26/2024	(Devices) What’s PIO?
Published	12/26/2024	(Devices) What’s polling?
Published	12/26/2024	(Devices) What is DMA conceptually?
Published	12/26/2024	(Devices) Is the DMA used for data transfer or for control information?
Published	12/26/2024	What is a device driver conceptually?
Published	12/26/2024	(Devices) How is the transmission of data between OS and device structured in memory?
Published	12/26/2024	(Devices) What should the CPU do before and after a DMA to avoid cache problems? (Direct memory access of a device)
Published	12/26/2024	(Devices) What is PCI?
Published	12/26/2024	(Devices) Is communication with hardware sync or async?
Published	12/26/2024	(Devices) What do DMA descriptor rings do? (= a circular buffer)
Published	12/26/2024	(Devices) What are the 4 things a device driver need to do?
Status	Last Update	Fields